There are numerous applications in which it is desired to selectively deposit semiconductor material onto a semiconductor surface relative to other surfaces. For instance, it can be desired to epitaxially form one or both of silicon and germanium on a semiconductor surface. A prior art method of epitaxially forming semiconductor material over a semiconductor surface is described with reference to FIGS. 1-3.
FIG. 1 shows a semiconductor wafer fragment 10 at a preliminary processing stage. Fragment 10 comprises a semiconductor substrate 12. Substrate 12 can comprise, consist essentially of, or consist of monocrystalline silicon. The silicon can be appropriately doped with one or more conductivity-enhancing dopants. For instance, the silicon can be lightly background doped with p-type dopant, and can comprise various conductively-doped diffusion regions (not shown) formed therein. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. The term “semiconductor material” refers to a material comprising one or more of the semiconductive elements, such as, for example, a material comprising one or both of silicon and germanium.
An electrically insulative material 14 is formed over substrate 12. Material 14 can comprise, consist essentially of, or consist of silicon and one or both of oxygen and nitrogen. For instance, material 14 can comprise silicon dioxide, silicon nitride, and/or silicon oxynitride. In the illustrated example, substrate 12 has an upper surface 13, and material 14 is formed directly against (i.e., in physical contact with) the upper surface 13. Material 14 is patterned to have a gap 16 extending therethrough to the upper surface 13 of substrate 12. Material 14 has exposed surfaces 15.
Referring to FIG. 2, a semiconductor material 18 is formed within gap 16 and also over the surfaces 15 of insulative material 14. Material 16 will typically comprise, consist essentially of, or consist of one or both of silicon and germanium. If material 16 comprises, consists essentially of, or consists of silicon, such material can be formed utilizing dichlorosilane, H2 and HCI. The dichlorosilane provides a silicon source. The H2 participates in the silicon deposition, and also can remove undesired oxides forming over the growing silicon. The HCI etches material 18 before the material can form a uniform layer over insulative material 14. Specifically, the material 18 nucleates over insulative material 14 to form small islands on surface 15, as shown. The HCI continuously etches material 18 from the small islands, and accordingly removes material 18 from the islands before the islands can merge to form a continuous layer. The HCI is also thought to remove material 18 which is growing over surface 13 (the shown material 18 within gap 16), but such removal is too slow to prevent the layer of material 18 from forming within gap 16. Accordingly, the HCI effectively creates a selective deposition of material 18 over the surface 13 of semiconductor material 12 relative to the surfaces 15 of insulative material 14. The HCI can be replaced with Cl2 in some aspects of the prior art.
FIG. 3 shows construction 10 at the conclusion of the epitaxial growth, and shows that the semiconductor material 18 has been selectively formed over surface 13 of semiconductor substrate 12 relative to surfaces 15 of insulative material 14.
A problem with the processing of FIGS. 1-3 is that the utilization of HCI significantly slows the rate of deposition of semiconductor material 18 relative to a rate which would occur in the absence of the HCI. Accordingly, it is desired to develop deposition processes which can selectively form a semiconductor material over an exposed semiconductor substrate surface relative to exposed surfaces of non-semiconductor materials, and which have a higher rate than the processing sequence of FIGS. 1-3.
The processing sequence of FIGS. 1-3 is an exemplary prior art process. Other processes have been developed which are modifications of the process described with reference to FIGS. 1-3. For instance, in one modification a semiconductor precursor (such as, for example, dichlorosilane) is provided in combination with H2 to form semiconductor material 18 over a surface of a semiconductor substrate and over surfaces of insulative materials. After the growth of the semiconductor material, HCI is provided to selectively remove the semiconductor material from over the insulative materials surfaces while leaving a layer of the semiconductor material over the semiconductor substrate surface. In some aspects, the cycling of deposition of semiconductor material, etching of semiconductor material from over insulative material surfaces, deposition of the material, etching of the material, etc., is repeated multiple times to form a semiconductor material to a desired thickness over a semiconductor substrate surface. A particular prior art methodology flows disilane for about 10 seconds, then Cl2 for about 10 seconds, then H2 for about 10 seconds, and repeats the process multiple times to form a semiconductor layer to a desired thickness over a semiconductor substrate surface.
FIGS. 4 and 5 illustrate another exemplary prior art application for selective formation of epitaxially-grown semiconductor material over a semiconductor substrate. Referring initially to FIG. 4, a wafer fragment 20 comprises a substrate 22. Substrate 22 can comprise the same construction as described previously relative to substrate 12 of FIG. 1, and accordingly can comprise monocrystalline silicon lightly-background doped with p-type dopant. Substrate 22 comprises an upper surface 23.
An isolation region 24 extends within substrate 22. Isolation region 24 can comprise, for example, a shallow trench isolation region, and accordingly can comprise silicon dioxide. Isolation region 24 comprises an upper surface 25.
A transistor gate 26 is formed over surface 23 of substrate 22. Transistor gate 26 comprises an insulative material 28, a conductive material 30, and an insulative cap 32. Insulative material 28 can comprise, for example, silicon dioxide, and can be referred to as pad oxide. Conductive material 30 can comprise, for example, one or more of metal, metal compounds and conductively-doped semiconductor material (such as, for example, conductively-doped silicon). Insulative cap 32 can comprise, consist essentially of, or consist of silicon together with one or both of oxygen and nitrogen. For instance, insulative cap 32 can comprise, consist essentially of, or consist of silicon dioxide, silicon nitride, or silicon oxynitride. Insulative cap 32 comprises an upper exposed surface 33.
An anisotropically-etched sidewall spacer 34 is along a sidewall of transistor gate 26. Spacer 34 can comprise, consist essentially of, or consist of silicon together with one or both of oxygen and nitrogen. Accordingly, spacer 34 can comprise, or consist essentially of, or consist of one or more of silicon dioxide, silicon nitride and silicon oxynitride. Spacer 34 has an exposed surface 35.
A conductively-doped diffusion region 36 extends within substrate 22 beside transistor gate 26. The conductively-doped diffusion region 36 and transistor gate 26 can be together incorporated into a transistor device.
Referring to FIG. 5, a semiconductor material 38 is formed over surface 23 of semiconductor substrate 22 selectively relative to surfaces 25 and 33 of insulative materials 24 and 32, respectively. Semiconductor material 38 can comprise, consist essentially of, or consist of one or both of silicon and germanium, and can be formed utilizing processing analogous to that described previously with reference to FIGS. 1-3. Accordingly, the semiconductor material can be formed by deposition from a semiconductor precursor in combination with an etch which removes the deposited material from over surfaces 25 and 33 while leaving the material over surface 23. An undesired consequence of the etch is that such rounds an outer corner of deposited material 38, as can be seen at a location 40 in the diagram of FIG. 5. The rounded outer corner can be referred to as a faceted corner, and can increase degradation of a transistor device component (with a common effect being p-channel degradation), and can also adversely affect an implant profile if a dopant is implanted either into or through semiconductor material 38. For instance, conductively-doped diffusion region 36 would sometimes be formed by an implant subsequent to formation of material 38 rather than being present prior to deposition of semiconductor material 38. The rounded faceted corner 40 could then adversely affect formation of the diffusion region 36.
The semiconductor material 38 of FIG. 5 can ultimately be conductively doped, and can be incorporated into, for example, an elevated source/drain region associated with a transistor device comprising gate 26.
Numerous problems are encountered during the processing described above with reference to FIGS. 1-5. Such problems include the faceted corner 40 and slow growth rate discussed previously. Another problem is that the deposition rate and quality can be sensitive to the amount of etchant (such as, for example, HCI) utilized during the deposition/etch processing, which can make it problematic to control wafer throughput and quality in a fabrication process. For instance, it is sometimes found that increasing HCI flow by 10% will decrease the growth rate of a deposited semiconductor material by about 20%. It would be desirable to develop deposition methods which alleviate, and preferably eliminate, some or all of the above-discussed problems.